A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan

The demand for high performance system-on-chips (SoC) in communication and computing has been growing continuously. To meet the performance goals, very aggressive circuit design techniques such as the use of smallest possible logic depth are being practiced. Replacement of normal flip-flops with scan flip-flops adds an additional multiplexer delay to critical path. Furthermore as the combinational depth decreases, the performance degradation caused by scan multiplexer delay become more critical. Elimination of the scan multiplexer delay off the functional path has become crucial in maintaining the circuit performance. In this work we propose a new transistor level scan cell design to eliminate the scan multiplexer off the functional path. The proposed scan cell uses separate master latch for functional and test mode where as the slave latch is same in both the modes. Our proposed scan flip-flop fully comply with the conventional test flow. Post layout experimental results justify the effectiveness of the proposed scan cell design in eliminating the performance penalty of scan, and thus in improving the timing performance of integrated circuits

A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test

Over the years, serial scan design has became the defacto Design for Testability (DFT) technique. The ease of testing and high test coverage has made it to gain wide spread industrial acceptance. However, there are associated penalties with serial scan. These penalties include performance degradation, test data volume, test application time, and test power dissipation. The performance overhead of scan design is due to the scan multiplexers added to the inputs of every flip-flop. In today's very high speed designs with minimum possible combinational depth, the performance degradation caused by scan multiplexer has became magnified. Hence to maintain the circuit performance the timing overhead of scan design must be addressed. In this paper we propose a new scan flip-flop design that eliminates the performance overhead of serial scan. The proposed design removes the scan multiplexer off the functional path. The proposed design can help in improving the functional frequency of performance critical designs. Furthermore, the proposed design can be used as a common scan flip-flop in mixed mode scan test wherein it can be used as a serial scan cell as well as random access scan (RAS) cell

Graph theoretic approach for scan cell reordering to minimize peak shift power

Scan circuit testing generally causes excessive switching activity compared to normal circuit operation. This excessive switching activity causes high peak and average power consumption. Higher peak power causes, supply voltage droop and excessive heat dissipation. This paper proposes a scan cell reordering methodology to minimize the peak power consumption during scan shift operation. The proposed methodology first formulate the problem as graph theoretic problem then solve it by a linear time heuristic. The experimental results show that the methodology is able to reduce up to 48% of peak power in compared to the solution provided by industrial tool

A Cost Effective Technique for Diagnosis of Scan Chain Faults

Scan based diagnosis plays a critical role in failure mode analysis for yield improvement. However, as the logic circuitry associated with scan chains constitute a significant fraction of a chip's total area the scan chain itself can be subject to defects. In some cases, it has been observed that scan chain failures may account up to 50% of total chip failures. Hence, scan chain testing and diagnosis have become very crucial in recent years. This paper proposes a hardware-assisted low complexity and area efficient scan chain diagnosis technique. The proposed technique is simple to implement and provides maximum diagnostic resolution for stuck-at faults. The proposed technique can be further extended to diagnose scan chain's timing faults

On Minimization of Peak Power for Scan Circuit during Test

Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current which results into supply voltage droop and eventually yield loss. This paper proposes an efficient methodology for test vector re-ordering to achieve minimum peak power supported by the given test vector set. The proposed methodology also minimizes average power under the minimum peak power constraint. A methodology to further reduce the peak power, below the minimum supported peak power, by inclusion of minimum additional vectors is also discussed. The paper defines the lower bound on peak power for a given test set. The results on several benchmarks shows that it can reduce peak power by up to 27%

Revisiting Random Access Scan for Effective hnhancement of Post-silicon Observability

Due to tremendous growth in complexity of modern designs, bugs inevitably escape the pre-silicon verification stage. This has led to considerable increase in the time and effort dedicated to post-silicon validation. Debugging designs at post silicon stage faces a severe bottleneck of limited observability of the internal states. This paper presents a methodology for post-silicon debug utilizing the special features of progressive random access scan (PRAS). The l'RAS offers a read-out of non-destructive scan values which is the bottleneck in the process of debugging. The proposed methodology avoids the large overhead of additional resources for debugging as the Der architecture is reused. PRAS provides a simultaneous solution to the problems of power, data volume and application time during testing at the cost of routing overhead. The PRAS based proposed architecture offers visibility of internal states in fewer clock cycles than traditional serial scan chain based debug methods. The proposed debug scheme offers reconfigurability which enables selective visibility of internal states of a certain portion of the design. Experimental results indicate the better performance of the proposed methodology as compared to the state restoration based observability enhancement techniques